Logisim-Evolution Part II
I forgot to bring my laptop charger with me over Thanksgiving, so I didn't make much progress. But I did have an epiphany: in the simulation, ganging 8 1-bit repeaters each with 8 1-bit registers is probably stupid-slow compared to 1 8-bit repeater with 8-8 bit registers.
So I went back to the drawing board and updated my multi-bit repeater and comparator models to use 1, 5, or 8 bit registers. to match my bus sizes, and lo, Logisim now simulates Redstone faster than Minecraft Bedrock edition, although not by much; it maxes out around 15Hz redstone clock so about a 50% improvement over Bedrock.
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| Calculating the 16bit Fibonacci Sequence |
I also started building a simple monitor circuit.
And I updated my assembler to output machine code to the console so it can be loaded into the Logisim ROM component.
But even better, I discovered that Logisim can synthesize VHDL. And I discovered that GHDL can compile VHDL into Linux executable programs.
Most logic simulation systems are interpreted; it's basically just a loop with a really big IF/ELSE that conditionally updates nodes. There's different ways to implement it, but effectively that's what it boils down to; interpreting VHDL step by step like it was BASIC or Python or something. And worse, Logisim is written in Java so the simulator itself in interpreted, (JIT compilation not withstanding).
GHDL takes a different approach and compiles VHDL into native x86-64 machine code ahead of time. The performance advantages should be intuitively obvious. Compiled code is pretty much always faster than interpreted code. It's Bedrock vs Java Edition.
$ head -n20 vhdl/toplevel/logisimTopLevelShell_behavior.vhd
--==============================================================================
--== Logisim-evolution goes FPGA automatic generated VHDL code ==
--== https://github.com/logisim-evolution/ ==
--== ==
--== ==
--== Project : attarc_vhdl ==
--== Component : logisimTopLevelShell ==
--== ==
--==============================================================================
ARCHITECTURE platformIndependent OF logisimTopLevelShell IS
-----------------------------------------------------------------------------
-- Here all used components are defined --
-----------------------------------------------------------------------------
COMPONENT logisimTickGenerator
GENERIC ( nrOfBits : INTEGER;
reloadValue : INTEGER );
PORT ( FPGAClock : IN std_logic;
FPGATick : OUT std_logic );
...I can possibly save myself quite a bit of work by not having to write a software emulator, if the VHDL simulation is performant and useful enough.
After some fiddling around and RTFMing, I got GHDL to compile my VHDL to an executable!
...
In the meantime I am not unhappy with the 15hz redstone clock performance of ATTARC under Logisim. It's 50% faster than Bedrock and way easier to build, modify, and validate circuits. I will probably use this going forward to validate my ideas before building them in Minecraft.
I will probably still write a software emulator, eventually, for performance reasons. An emulator can completely disregard the hardware implementation details as long as it follows the interface specification; it's a black box. This makes it much simpler internally than a full logic-level simulation. For example, instead of simulating shift registers we can just use setTimeout to make something happen later and let the OS worry about the timing. Clearly this is a lot less work for the host CPU.
Having the working hardware simulator will be very useful for validating the emulator.
Plus, now the door is open to burning ATTARC onto an FPGA. I'm kind of excited about the idea of my Minecraft CPU coming to life in the real world. And running at 10's or 100's of MHz :)
Stay tuned...
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