ATTARC - Advanced TTA for Redstone Computing

I found a bug in my original model; it extends pulses that are already extended. That's what I get for publishing it at 2am. Also I forgot my power cord for my laptop over Thanksgiving so I was reduced to developing the new model in Circuitverse. You can  see this design gets it right by using a counter to enforce minimum pulse lengths without extending pulses that already meet that minimum. I haven't implemented locking yet. Anyway this model is overkill for 1-tick repeaters which is what most repeaters are. Who's locking repeaters with more than 1 tick delay anyhow?

I forgot to bring my laptop charger with me over Thanksgiving, so I didn't make much progress. But I did have an epiphany: in the simulation, ganging 8 1-bit repeaters each with 8 1-bit registers is probably stupid-slow compared to 1 8-bit repeater with 8-8 bit registers. So  I went back to the drawing board and updated my multi-bit repeater and comparator models to use 1, 5, or 8 bit registers. to match my bus sizes, and lo, Logisim now simulates Redstone faster than Minecraft Bedrock edition, although  not by much; it maxes out around 15Hz redstone clock so about a 50% improvement over Bedrock. Calculating the 16bit Fibonacci Sequence I also started building a simple monitor circuit. And I updated my assembler to output machine code to the console so it can be loaded into the Logisim ROM component. $ npm run asm './examples/fib16-2-opt.js'  > fib16opt2.hex But even better, I discovered that Logisim can synthesize VHDL. And I discovered that GHDL can compile VHDL into...