Posts

An Improved model of the Minecraft Repeater

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I found a bug in my original model; it extends pulses that are already extended. That's what I get for publishing it at 2am. Also I forgot my power cord for my laptop over Thanksgiving so I was reduced to developing the new model in Circuitverse. You can  see this design gets it right by using a counter to enforce minimum pulse lengths without extending pulses that already meet that minimum. I haven't implemented locking yet. Anyway this model is overkill for 1-tick repeaters which is what most repeaters are. Who's locking repeaters with more than 1 tick delay anyhow?

Logisim-Evolution Part II

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I forgot to bring my laptop charger with me over Thanksgiving, so I didn't make much progress. But I did have an epiphany: in the simulation, ganging 8 1-bit repeaters each with 8 1-bit registers is probably stupid-slow compared to 1 8-bit repeater with 8-8 bit registers. So  I went back to the drawing board and updated my multi-bit repeater and comparator models to use 1, 5, or 8 bit registers. to match my bus sizes, and lo, Logisim now simulates Redstone faster than Minecraft Bedrock edition, although  not by much; it maxes out around 15Hz redstone clock so about a 50% improvement over Bedrock. Calculating the 16bit Fibonacci Sequence I also started building a simple monitor circuit. And I updated my assembler to output machine code to the console so it can be loaded into the Logisim ROM component. $ npm run asm './examples/fib16-2-opt.js'  > fib16opt2.hex But even better, I discovered that Logisim can synthesize VHDL. And I discovered that GHDL can compile VHDL into...

Simulating ATTARC With Logisim-Evolution

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My next step for this project is to develop an emulator of some sort to speed software development and debugging. Minecraft computers are very slow, even ATTARC, and I can produce working software faster with a system that will run it faster. For example, in Minecraft it takes ATTARC about 5 minutes to calculate the Fibonacci sequence to 16 bits. Reminds me of the bad old days when I would run "make" and get a cup of coffee. My first thought was to write a software virtual machine. ATTARC is a trivial architecture so that should not be too difficult. But as I sat down to start coding I realized that, while I could produce a simple emulator that runs the code as fast as possible and NOT simulating timing hazards, it would need to be cycle-accurate to really validate software, and it would take a lot more work to make it "cycle-accurate". Nothing I can't handle, but it does bump up the complexity, So then I got to wondering if there might be an existing simulation...

Testing a Logisim-Evolution model of Minecraft redstone repeater

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UPDATE: Dec 1, 2024 There is a bug in the configurable-delay model; it re-extends pulses that are already extended. It's fine as long as you don't put more than one >= 2-tick delay-repeater in series. I have created an improved model here  https://attarc-redstone.blogspot.com/2024/12/an-improved-model-of-minecraft-repeater.html

Calculating the Fibonacci sequence using 16 bit words on ATTARC 1.0

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 This video demonstrates the ATTARC CPU calculating the Fibonacci sequence using 16 bit words. You'll probably want to speed it up. Source code for assembly program (assembler & linker & ROM programmer implemented in JavaScript) // calculate 16 bit Fibonacci sequence import { ZERO , NULL , INVERT , ISZERO , ADD1_C , R0JC , R1 , R2 , R3 , R4 , R5 , R6 , R7SC , PC , LOG_A , LOG_B , ADD1_A , ADD1_B , XOR , AND , OR , ADD1 , RNG , Program } from "../asm" ; const P = new Program (); export default P ; P . clear ( ADD1_A ) . clear ( ADD1_B ) . clear ( ADD1_C ) . clear ( R0JC ) // 1L . clear ( R1 ) // 1L . clear ( R2 ) // 1H . move ( 1 , R3 ) // 2L . clear ( R4 ) // 2H . add ( R1 , R3 , R1 ) . label ( 'loop' ) . addc ( R2 , R4 , R2 ) . jumpcnz ( 'halt' ) . add ( R1 , R3 , R3 ) . addc ( R2 , R4 , R4 ) . jumpcnz ( 'halt' ) . add ( R1 , R3 , R1 ) . addc ( R2 , R4 , R2 ) ...

Introducing ATTARC: Advanced Transport Triggered Architecture for Redstone Computing

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One day I got bored of playing Minecraft survival, and I decided to build a redstone computer. ATTARC 1.0 Given my background as a computer engineer and the many helpful Redstoners in the community, this seemed like a fairly achievable goal. Still, I had never previously designed a CPU from scratch; I'm old-school but not quite that old. But I was confident that I had the requisite knowledge and experience, so I began the design process. I started by asking myself this question: "What does a computer fundamentally DO?" The answer in my head: "It shuffles bits around". So I decided I could just build a bus, some registers, attach some peripherals, decoders, a program counter, and some ROM, and it would be a brilliantly simple but powerful and flexible computer. Then I thought to myself, "Somebody else must have already thought of this." Sure enough, somebody had, and it even had it's own wikipedia page: https://en.wikipedia.org/wiki/Transport_trigge...